The present invention relates generally to a method and an apparatus for data transmission and reception and more specifically to a method and an apparatus in which an offset voltage may be prevented on a floating capacitance in a connection node between a first transfer device and a second transfer device.
A conventional semiconductor memory device may have a column select transfer gate for transferring a data bit signal amplified in a sense amplifier to a data bus.
Referring now to FIG. 1, a portion of conventional semiconductor memory device is set forth in a schematic diagram and given the general reference character 100.
Conventional semiconductor memory device 100 is formed on a semiconductor substrate 10S. Conventional semiconductor memory device 100 includes a column select transfer gate circuit 11 connected to data buses (IOT and ION) and bit line pairs (D1 and DB1 to Dn AND DBn). Transfer gate circuit 11 also is connected to receive column select signal PYU and column select signals (YL1 to YLn). Column select transfer gate circuit 11 is arranged such that column select transfer gates (M1i and M2i) are connected in series between bit line Di and column select transfer gates (M1Bi and M2Bi) are connected in series between bit line DBi (i can be a number between 1 and n, where n is the number of columns of memory cells illustrated). N-type MOSFETs (metal oxide semiconductor field effect transistors) are used for column transfer gates (M1i, M2i, M1Bi, and M2Bi). A bit line pair (Di and DBi) transmits complementary binary data signals indicating the logic value of one data bit.
A parasitic capacitor (Ci and CBi) is formed at the connection point of series connected column select transfer gates (M1i-M2iand M1Bi-M2Bi) and is illustrated having one node connected to the connection point and another node connected to ground.
A column address decode circuit 13 receives and address signal from a command bus pad 10CMD and generates column select signal PYU and column select signals (YL1 to YLn). Column select signal PYU is received at a gate of each column select transfer gate (M11 to M1n and M1B1 to M1Bn). Column select signal YLi is received at a gate of each column select transfer gate (M2iand M2Bi). Column select signal PYU and column select signal YLi are supplied simultaneously from address decode circuit 13. Address decode circuit 13 decodes a column address received with an access command when accessing conventional semiconductor memory device 100.
A sense amplifier Si is connected between bit line pair (Di and DBi). Bit line Di is electrically connected to data bus IOT when column select transfer gates (M2i and M1i) are turned on. Bit line DBi is electrically connected to data bus ION when column select transfer gates (M2Bi and M1Bi) are turned on.
Data buses (IOT and ION) are connected to a precharge circuit 15 and data bus pad 10DB on semiconductor substrate 10S.
A description of the operation of conventional semiconductor memory device 100 will now be described with reference to FIGS. 1 and 2. FIG. 2 is a timing diagram illustrating the operation of conventional semiconductor memory device 100 for various cycles. Column select transfer gates (M1i, M2i, M1Bi, and M2Bi) of conventional semiconductor memory device 100 operate as follows.
When no access to the conventional semiconductor memory device 100 is taking place, column address decode circuit 13 outputs column select signal PYU and column select signal YLi having a low level.
With column select signal PYU and column select signal YLi at a low level, column select transfer gates (M1i, M2i, M1Bi, and M2Bi) are all turned off and bit line pair (Di and DBi) are not electrically connected to data buses (IOT and ION), respectively.
When a write command W is received by conventional semiconductor memory device 100 as an external input command, a column address in the write command (W in FIG. 2) is supplied to column address decode circuit 13 through command bus pad 10CMD. Column address decode circuit 13 generates a column select signal PYU and column select signal YLi having a high level accordingly.
With column select signal PYU and column select signal YLi at a high level, column select transfer gates (M1i, M2i, M1Bi, and M2Bi) are all turned on and bit line pair (Di and DBi) are electrically connected to data buses (IOT and ION), respectively. In this way, data may be transferred from data buses (IOT and ION) to bit line pair (Di and DBi) and written into a memory cell (not shown) that is connected to bit line pair (Di and DBi) and that has already been turned on in response to a row address.
Subsequently, at the end of the write operation, column select signal PYU and column select signal YLi are simultaneously switched from the high level to the low level. With column select signal PYU and column select signal YLi at a low level, column select transfer gates (M1i, M2i, M1Bi, and M2Bi) are all turned off and bit line pair (Di and DBi) are not electrically connected to data buses (IOT and ION), respectively. In this way, connection nodes having parasitic capacitors (Ci and CBi) become floating and charge stored on parasitic capacitors (Ci and CBi) becomes trapped or stored.
Subsequently, the data buses (IOT and ION) are precharged with precharge circuit 15 in response to a precharge command (P in FIG. 2) supplied through command bus pad 10CMD. Data busses (IOT and ION) are precharged to an intermediate level (precharge level). However, at this time, connection nodes having parasitic capacitors (Ci and CBi) remain floating and can have different voltages in accordance with the logic value of data previously written.
Subsequently, when a read command (R in FIG. 2) is received by conventional semiconductor memory device 100, address decode circuit 13 supplies a column select signal PYR and column select signal YLi having a high level in response to a column address.
In the read command, a row address is supplied to a row address decode circuit (not shown) and a row of memory cells (not shown) are selected. Sense amplifiers (S1 to Sn) amplify data received from the memory cells. Thus, a row of memory cells is simultaneously selected.
When column select signals (PYR and YLi) become high, the connection nodes having parasitic capacitors (Ci and CBi) become electrically connected to bit line pair (Di and DBi) and data buses (IOT and ION). Because parasitic capacitors (Ci and CBi) can have different voltage potentials as previously described, an offset voltage can be produced on the data buses (IOT and ION). This offset can affect the access speed and/or logic integrity of data supplied from sense amplifier Si and read out on data buses (IOT and ION).
Japanese Laid-Open Patent Publication No. 2000-149571 (JP 2000-149571) discloses a conventional semiconductor integrated circuit device.
JP 2000-149571 discloses a conventional semiconductor integrated circuit device including bit line pairs divided into groups having different capacitance values. A charge transfer device is included to separate bit line pairs. The charge transfer device is switched off before electric charge is provided to bit line pairs and a sense amplifier in a read operation.
A reference electric potential supply circuit is provided and a charge transfer device is switched on to provide charge to a connection point including a parasitic capacitor (for example, Ci and CBi). Then the other charge transfer device is turned on to supply electric charge to a detection/amplification line.
However, similarly as discussed above, the conventional semiconductor integrated circuit device disclosed in JP 2000-149571 has a drawback in that after a write operation in which data is written, electric charge is stored or trapped on capacitors (Ci and CBi) which are floating. During a subsequent read cycle, the signal provided by the electric charge is stored or trapped on capacitors (Ci and CBi) can be superimposed on the read data. If the data signal during a subsequent read cycle is complementary to the trapped charge on capacitors (Ci and CBi), which can correspond to the logic levels of the previous write data, then the read data can have an offset. This problem is illustrated in FIG. 2 on data buses IOT and ION during the read cycle R.
As can be seen, the electric charge stored on capacitors (Ci and CBi) needs to be discharged before the read operation so that an offset does not occur.
JP 2000-149571 is adapted so that the transistor disposed between the detection/amplification line and electric charge transfer devices is turned off. Then electric charge indicating a logic value of information stored is supplied to the connection point between two electric charge transfer devices and the transistor on the side of the detection/amplification line is switched on to supply the electric charge to the detection/amplification line.
The electric charge described above is used to detect and amplify the logic value of information stored in the memory cell and is not applied to discharge or precharge the electric charge stored on capacitors (Ci and CBi).
In light of the above discussion, it would be desirable to provide a method and an apparatus for data transmission and reception that may include signal transfer devices connected in series that may be activated to transfer data in a first data transfer direction. Thereafter, electric charge stored on parasitic capacitors at the connection point of the signal transfer devices may be precharged. In this way, a subsequent data transfer in the opposite direction may not be adversely affected.
A method and apparatus for data transmission and reception according to the present embodiments may include a data transmission and reception apparatus that may allow data to be transferred between a data bus and a bit line pair. The data transmission/reception apparatus may include a column select transfer gate circuit that may receive column select signals from a column address decode circuit. The column select transfer circuit may include a transfer gate circuit that may provide a data transmission/reception path between a data bus and a bit line pair. Transfer gate circuit may include connection nodes that may have parasitic capacitors. A precharge circuit may allow previous data signals to be removed during a precharge operation before a subsequent data transfer operation is executed. In this way, an offset voltage may be eliminated from the data signal and data integrity may be improved.
According to one aspect of the embodiments, a method for data transmission/reception may include activating essentially simultaneously a first signal transfer device and a second signal transfer device electrically connected in series to provide a data transfer path between a first data transmission/reception apparatus and a second data transmission/reception apparatus. After bringing the second signal transfer device into a second signal transfer device data transfer interrupt state, an electric potential may be set on a parasitic capacitor at a connection point between the first signal transfer device and the second signal transfer device. Upon completion of setting the electric potential, the first signal transfer device may be brought into a first signal transfer device data interrupt state.
According to another aspect of the embodiments, data being transmitted may have data values represented by first and second electric potential levels. Setting the electric potential may include precharging the electric potential at the connection point to a precharge level between the first and second electric potential levels after bringing the second signal transfer device into the second signal transfer device data interrupt state.
According to another aspect of the embodiments, precharging may include precharging a first data transmission/reception data line to essentially the electric potential within a time period. The time period being after a second signal transfer device is in a second signal transfer device data transfer interrupt state, and before the first signal transfer device is in a first signal transfer device data transfer interrupt state.
According to another aspect of the embodiments, the transmission of data between the first data transmission/reception apparatus and the second data transmission apparatus may be achieved by essentially simultaneously transmitting complementary data values.
According to another aspect of the embodiments, the second data transmission/reception apparatus may be a semiconductor memory having data transmitted on a bit line electrically connected to the second signal transfer device. The first data transmission/reception apparatus may include a first data transmission/reception data line electrically connected to the first signal transfer device. Precharging may include precharging a first data transmission/reception data line to essentially the electric potential during a time period from bringing the second signal transfer device into the second signal transfer device data transfer interrupt state to bringing the first signal transfer device into the first signal transfer device data transfer interrupt state.
According to another aspect of the embodiments, an apparatus for data transmission/reception in which data may be transferred between a second data transmission/reception apparatus and a first data transmission/reception apparatus through a first signal transfer device and a second signal transfer device electrically connected in series may include a first data transfer passage electrically connected to the first data transmission/reception apparatus and the first signal transfer device. The second signal transfer device may be electrically connected between the first signal transfer device and the second data transmission/reception apparatus. The first signal transfer device and the second signal transfer device may be activated essentially simultaneously to transfer data from the first data transmission/reception apparatus to the second data transmission/reception apparatus. Data being transferred may have data values represented by first and second electric potential levels. A transfer device control circuit may supply a second control signal coupled to a control terminal of the second signal transfer device and a first control signal coupled to a control terminal of the first signal transfer device. The second control signal may disable the second signal transfer device a predetermined time before the first control signal disables the first signal transfer device after the transfer of data. A precharge circuit may be coupled to supply a precharge level that may be between the first and second electric potential levels to the first data transfer passage during the predetermined time before the first control signal disables the first signal transfer device after the transfer of data.
According to another aspect of the embodiments, the precharge circuit may begin supplying the precharge level to the first data transmission passage after the second control signal disables the second signal transfer device.
According to another aspect of the embodiments, the precharge circuit may precharge the first data transmission passage to essentially the precharge level during the predetermined time before the first control signal disables the first signal transfer device.
According to another aspect of the embodiments, the transfer of data may include transferring complementary data signals.
According to another aspect of the embodiments, a third signal transfer device may be connected in parallel with the first signal transfer device and may have a control terminal coupled to receive the first control signal.
According to another aspect of the embodiments, the first signal transfer device and the second signal transfer device may be insulated gate field effect transistors (IGFETs).
According to another aspect of the embodiments, the first data transfer passage, the first signal transfer device, the second signal transfer device, the second data transmission/reception apparatus, and the transfer device control circuit may be formed on a semiconductor substrate and an output of the first data transmission/reception apparatus may be coupled to a pad formed on the semiconductor substrate. The pad may be further coupled to the first data transfer passage.
According to another aspect of the embodiments, the precharge circuit may be formed on the semiconductor substrate and may supply the precharge level to the first data transfer passage in response to a precharge command received by at least one command pad formed on the semiconductor substrate.
According to another aspect of the embodiments, the first data transmission/reception apparatus may be a data processing apparatus. The second data transmission/reception apparatus may be a semiconductor memory device including a bit line electrically connected to the second signal transfer device. The first data transfer passage may be a data bus for transferring data between the data processing apparatus and the semiconductor memory device. The first control signal may be a first column select signal generated on the basis of at least a first portion of a column address supplied form the data processing apparatus to the semiconductor memory device. The second control signal may be a second column select signal generated on the basis of at least a second portion of the column address.
According to another aspect of the embodiments, an apparatus for data transmission/reception may include a transfer circuit including a first signal transfer device and a second signal transfer device electrically connected in series to provide a first data transfer path between a first data transmission/reception apparatus and a second data transmission/reception apparatus. A transfer device control circuit may be coupled to the transfer circuit. The transfer device control circuit may activate the first and second signal transfer devices to transfer data from the first data transmission/reception apparatus to the second data transmission/reception apparatus and may disable the second signal transfer device a predetermined time before disabling the first signal transfer device after the data transfer. A precharge circuit may be coupled to supply a precharge level to a first connection node between the first signal transfer device and second signal transfer device during the predetermined time.
According to another aspect of the embodiments, the precharge level may be supplied through the first signal transfer device to the first connection node.
According to another aspect of the embodiments, the first signal transfer device may be electrically connected to a first data line of the first data transmission/reception apparatus and the second signal transfer device may be electrically connected to a second data line of the second data transmission/reception apparatus. The precharge circuit may supply the precharge level to the first data line.
According to another aspect of the embodiments, the transfer circuit may include a third signal transfer device and a fourth signal transfer device electrically connected in series to provide a complementary first data transfer path between the first data transmission/reception apparatus and the second data transmission/reception apparatus. The transfer device control circuit may be coupled to the transfer circuit. The transfer device control circuit may activate the third and fourth signal transfer devices to transfer data from the first data transmission/reception apparatus to the second data transmission/reception apparatus and may disable the fourth signal transfer device the predetermined time before disabling the third signal transfer device after the data transfer. The precharge circuit may be coupled to supply the precharge level to a second connection node between the third signal transfer device and the fourth signal transfer device during the predetermined time. The third signal transfer device may be electrically connected to a complementary first data line of the first data transmission/reception apparatus. The fourth signal transfer device may be electrically connected to the complementary second data line of the second data transmission/reception apparatus. The precharge circuit may supply the precharge level to the complementary first data line.
According to another aspect of the embodiments, the transfer device control circuit may be a column address decoder circuit.
According to another aspect of the embodiments, data may be transmitted in a complementary fashion having a first potential and a second potential and the precharge level may be between the first and second potentials.